master's thesis
Implementation of the synchronous counter on the FPGA device

Ivan Jurešić (2018)
University of Rijeka
Faculty of Engineering
Department of Automation and Electronics
Section of Electronics, Robotics and Automation
Cite this document...

Jurešić, I. (2018). Implementacija sinkronog brojila na FPGA sklopu (Master's thesis). Retrieved from https://urn.nsk.hr/urn:nbn:hr:190:142264

Jurešić, Ivan. "Implementacija sinkronog brojila na FPGA sklopu." Master's thesis, University of Rijeka, Faculty of Engineering, 2018. https://urn.nsk.hr/urn:nbn:hr:190:142264

Jurešić, Ivan. "Implementacija sinkronog brojila na FPGA sklopu." Master's thesis, University of Rijeka, Faculty of Engineering, 2018. https://urn.nsk.hr/urn:nbn:hr:190:142264

Jurešić, I. (2018). 'Implementacija sinkronog brojila na FPGA sklopu', Master's thesis, University of Rijeka, Faculty of Engineering, accessed 23 March 2019, https://urn.nsk.hr/urn:nbn:hr:190:142264

Jurešić I. Implementacija sinkronog brojila na FPGA sklopu [Master's thesis]. Rijeka: University of Rijeka, Faculty of Engineering; 2018 [cited 2019 March 23] Available at: https://urn.nsk.hr/urn:nbn:hr:190:142264

I. Jurešić, "Implementacija sinkronog brojila na FPGA sklopu", Master's thesis, University of Rijeka, Faculty of Engineering, Rijeka, 2018. Available at: https://urn.nsk.hr/urn:nbn:hr:190:142264