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undergraduate thesis
Izvedba aritmetičko-logičke jedinice 8-bitnog računala na FPGA sučelju
2019. urn:nbn:hr:190:294714
Ladić, Tin
University of Rijeka
Faculty of Engineering
Department of Computer Engineering
Section of Intelligent Computing Systems

Cite this document

Ladić, T. (2019). Izvedba aritmetičko-logičke jedinice 8-bitnog računala na FPGA sučelju (Undergraduate thesis). Rijeka: University of Rijeka, Faculty of Engineering. Retrieved from https://urn.nsk.hr/urn:nbn:hr:190:294714

Ladić, Tin. "Izvedba aritmetičko-logičke jedinice 8-bitnog računala na FPGA sučelju." Undergraduate thesis, University of Rijeka, Faculty of Engineering, 2019. https://urn.nsk.hr/urn:nbn:hr:190:294714

Ladić, Tin. "Izvedba aritmetičko-logičke jedinice 8-bitnog računala na FPGA sučelju." Undergraduate thesis, University of Rijeka, Faculty of Engineering, 2019. https://urn.nsk.hr/urn:nbn:hr:190:294714

Ladić, T. (2019). 'Izvedba aritmetičko-logičke jedinice 8-bitnog računala na FPGA sučelju', Undergraduate thesis, University of Rijeka, Faculty of Engineering, accessed 28 November 2024, https://urn.nsk.hr/urn:nbn:hr:190:294714

Ladić T. Izvedba aritmetičko-logičke jedinice 8-bitnog računala na FPGA sučelju [Undergraduate thesis]. Rijeka: University of Rijeka, Faculty of Engineering; 2019 [cited 2024 November 28] Available at: https://urn.nsk.hr/urn:nbn:hr:190:294714

T. Ladić, "Izvedba aritmetičko-logičke jedinice 8-bitnog računala na FPGA sučelju", Undergraduate thesis, University of Rijeka, Faculty of Engineering, Rijeka, 2019. Available at: https://urn.nsk.hr/urn:nbn:hr:190:294714

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Metadata
TitleIzvedba aritmetičko-logičke jedinice 8-bitnog računala na FPGA sučelju
Title (english)Realization of the 8-bit arithmetic-logic unit on the FPGA board
AuthorTin Ladić
MentorViktor Sučić (mentor)
Committee memberViktor Sučić (predsjednik povjerenstva)
GranterUniversity of Rijeka
Faculty of Engineering
(Department of Computer Engineering)
(Section of Intelligent Computing Systems)
Rijeka
Defense date and country2019-09-17, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Electrical Engineering
Abstract
U ovom radu obradio sam problematiku izrade Aritmetičko-logičke jedinice 8-bitnog računala. Kroz prikazivanje definicija osnovnih logičkih sklopova i osnovnih pravila pri zbrajanju i oduzimanju binarnih brojeva došao sam do načina implementacije 8-bitnog zbrajanja i oduzimanja kroz jednostavne logičke sklopove. Tu sam implementaciju, uz ostale funkcije ALU, pomoću programskog paketa Quartus prime opisao u jeziku za opis sklopovlja VHDL. Obavio sam simulaciju modeliranog sklopa i konfigurirao FPGA uređaj. Zbog potreba za unošenjem ulaznih vrijednosti i prikazom izlaznih vrijednosti iz FPGA sklopa dizajnirao sam i izradio ulazno/izlazni sklop na eksperimentalnoj pločici. Ulazno/izlazni sklop koristi GPIO konektor na DE10-Lite pločici. Testirao sam i uvjerio se u ispravan rad modeliranog sklopa aritmetičko-logičke jedinice.
Abstract (english)
This thesis focuses on implementing an 8-bit Arithmetic-logic unit (ALU) on the FPGA development board. Through using basic logic elements to implement binary adding and subtracting I found a way to accomplish 8-bit addition and subtraction. Using CAD software Quartus prime, I described an 8-bit Adder/Subtractor unit using hardware description language VHDL. I also described the other functions of the ALU (AND, OR, XOR, NOT) in the same way. Using simulation tools in Quartus prime I simulated the described logic circuit and determined that it functions correctly. After simulation I programmed the FPGA board. For interfacing the development board, I designed an input/output circuit on a prototype board. The input/output circuit connects to the development board using the GPIO connector. After assembly and testing I determined that the ALU works as intended.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:190:294714
Study programmeTitle: Undergraduate University Study of Electrical Engineering
Study programme type: university
Study level: undergraduate
Academic / professional title: sveučilišni/a prvostupnik/prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka elektrotehnike (sveučilišni/a prvostupnik/prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka elektrotehnike)
Type of resourceText
File originBorn digital
Access conditionsAccess restricted to students and staff of home institution
Terms of useLicence In copyright icon
Created on2020-08-31 09:51:47