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master's thesis
Implementacija sinkronog brojila na FPGA sklopu
2018. urn:nbn:hr:190:142264
Jurešić, Ivan
University of Rijeka
Faculty of Engineering
Department of Automation and Electronics
Section of Electronics, Robotics and Automation

Cite this document

Jurešić, I. (2018). Implementacija sinkronog brojila na FPGA sklopu (Master's thesis). Rijeka: University of Rijeka, Faculty of Engineering. Retrieved from https://urn.nsk.hr/urn:nbn:hr:190:142264

Jurešić, Ivan. "Implementacija sinkronog brojila na FPGA sklopu." Master's thesis, University of Rijeka, Faculty of Engineering, 2018. https://urn.nsk.hr/urn:nbn:hr:190:142264

Jurešić, Ivan. "Implementacija sinkronog brojila na FPGA sklopu." Master's thesis, University of Rijeka, Faculty of Engineering, 2018. https://urn.nsk.hr/urn:nbn:hr:190:142264

Jurešić, I. (2018). 'Implementacija sinkronog brojila na FPGA sklopu', Master's thesis, University of Rijeka, Faculty of Engineering, accessed 13 September 2024, https://urn.nsk.hr/urn:nbn:hr:190:142264

Jurešić I. Implementacija sinkronog brojila na FPGA sklopu [Master's thesis]. Rijeka: University of Rijeka, Faculty of Engineering; 2018 [cited 2024 September 13] Available at: https://urn.nsk.hr/urn:nbn:hr:190:142264

I. Jurešić, "Implementacija sinkronog brojila na FPGA sklopu", Master's thesis, University of Rijeka, Faculty of Engineering, Rijeka, 2018. Available at: https://urn.nsk.hr/urn:nbn:hr:190:142264

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Metadata
TitleImplementacija sinkronog brojila na FPGA sklopu
Title (english)Implementation of the synchronous counter on the FPGA device
AuthorIvan Jurešić
MentorNeven Bulić (mentor)
MentorViktor Sučić (komentor)
Committee memberViktor Sučić (predsjednik povjerenstva)
Committee memberLivio Šušnjić (član povjerenstva)
Committee memberAndrea Andrijašević (član povjerenstva)
GranterUniversity of Rijeka
Faculty of Engineering
(Department of Automation and Electronics)
(Section of Electronics, Robotics and Automation)
Rijeka
Defense date and country2018-10-05, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Electrical Engineering
Abstract
Ovim diplomskim radom prikazana je implementacija sinkronog brojila na FPGA sklopu. Prikazane su komponente od kojih se brojilo sastoji, te postupak njegovog projektiranja prema zadanom ciklusu brojanja. Prikazan je rad, te realizacija projektiranog brojila u VHDL programskom jeziku, unutar programa Quartus Prime, te je realizirano sinkrono brojilo implementirano na FPGA sklop na razvojnoj pločici DE10-Lite. Na kraju rada prikazani su elementi za izradu sklopa davača radnog takta i sklopa za prikaz stanja brojila, kao i sam proces dizajniranja tih sklopova.
Abstract (english)
This master’s thesis demonstrates the implementation of a synchronous counter on the FPGA. The components of which the counter consists, as well as the process of its design according to the given counting cycle are shown. The work and execution of the designed counter in the VHDL programming language is presented, within the Quartus Prime program, and a synchronous counter is implemented on the FPGA circuit on the DE10-Lite development board. At the end of the work, the elements of which clock generator and circuit for counter display consist are shown, as well as the design process of these circuits.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:190:142264
Study programmeTitle: Electrical Engineering
Study programme type: university
Study level: graduate
Academic / professional title: magistar/magistra inženjer/inženjerka elektrotehnike (magistar/magistra inženjer/inženjerka elektrotehnike)
Type of resourceText
File originBorn digital
Access conditionsAccess restricted to students and staff of home institution
Terms of useLicence In copyright icon
Created on2018-10-17 12:38:13