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undergraduate thesis
Implementacija 10-bitnog asinkronog brojila na FPGA platformi
2020. urn:nbn:hr:190:866500
Ilijanić, Luka
University of Rijeka
Faculty of Engineering
Department of Automation and Electronics
Section of Electronics, Robotics and Automation

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Ilijanić, L. (2020). Implementacija 10-bitnog asinkronog brojila na FPGA platformi (Undergraduate thesis). Rijeka: University of Rijeka, Faculty of Engineering. Retrieved from https://urn.nsk.hr/urn:nbn:hr:190:866500

Ilijanić, Luka. "Implementacija 10-bitnog asinkronog brojila na FPGA platformi." Undergraduate thesis, University of Rijeka, Faculty of Engineering, 2020. https://urn.nsk.hr/urn:nbn:hr:190:866500

Ilijanić, Luka. "Implementacija 10-bitnog asinkronog brojila na FPGA platformi." Undergraduate thesis, University of Rijeka, Faculty of Engineering, 2020. https://urn.nsk.hr/urn:nbn:hr:190:866500

Ilijanić, L. (2020). 'Implementacija 10-bitnog asinkronog brojila na FPGA platformi', Undergraduate thesis, University of Rijeka, Faculty of Engineering, accessed 10 November 2024, https://urn.nsk.hr/urn:nbn:hr:190:866500

Ilijanić L. Implementacija 10-bitnog asinkronog brojila na FPGA platformi [Undergraduate thesis]. Rijeka: University of Rijeka, Faculty of Engineering; 2020 [cited 2024 November 10] Available at: https://urn.nsk.hr/urn:nbn:hr:190:866500

L. Ilijanić, "Implementacija 10-bitnog asinkronog brojila na FPGA platformi", Undergraduate thesis, University of Rijeka, Faculty of Engineering, Rijeka, 2020. Available at: https://urn.nsk.hr/urn:nbn:hr:190:866500

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Metadata
TitleImplementacija 10-bitnog asinkronog brojila na FPGA platformi
Title (english)FPGA implementation of the 10-bit asynchronous counter
AuthorLuka Ilijanić
MentorIvan Volarić (mentor)
Committee memberViktor Sučić (predsjednik povjerenstva)
Committee memberIvan Volarić (član povjerenstva)
GranterUniversity of Rijeka
Faculty of Engineering
(Department of Automation and Electronics)
(Section of Electronics, Robotics and Automation)
Rijeka
Defense date and country2020-09-16, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Electrical Engineering
Abstract
U ovom završnom radu prikazana je implementacija 10-bitnog asinkronog brojila na FPGA platformi. Ciklus brojanja od 0 do 1023 prikazan je na četiri 7-segmentna pokazivača, uz mogućnost setiranja i resetiranja korištenjem dva tipkala na razvojnoj pločici DE10-Lite. Promjena stanja brojila ostvaruje se upravljačkim impulsom, koji se generira pomoću vremenskog sklopa 555 prilikom astabilnog načina rada. Modeliranje asinkronog brojila i pretvorba binarnog u BCD signal izvršeno je unutar programskog paketa Quartus Prime korištenjem VHDL programskog jezika.
Abstract (english)
In this final thesis is presented the implementation of a 10-bit asynchronous counter on the FPGA platform. The counting cycle from 0 to 1023 is displayed on four 7-segment displays, with the possibility of setting and resetting using two buttons on the DE10-Lite development board. The change of the counter state is realized by the clock pulse, which is generated by the 555 timer circuit in astable mode. The design of the asynchronous counter and the conversion of the binary to the BCD signal was performed within the Quartus Prime software using the VHDL programming language.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:190:866500
Study programmeTitle: Undergraduate University Study of Electrical Engineering
Study programme type: university
Study level: undergraduate
Academic / professional title: sveučilišni/a prvostupnik/prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka elektrotehnike (sveučilišni/a prvostupnik/prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka elektrotehnike)
Type of resourceText
File originBorn digital
Access conditionsAccess restricted to students and staff of home institution
Terms of useLicence In copyright icon
Created on2021-09-30 09:50:16