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undergraduate thesis
Izvedba aritmetičko-logičke jedinice 8-bitnog računala na FPGA sučelju
2023. urn:nbn:hr:190:030908
Rogić, Vid
University of Rijeka
Faculty of Engineering
Department of Automation and Electronics
Section of Electronics, Robotics and Automation

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Rogić, V. (2023). Izvedba aritmetičko-logičke jedinice 8-bitnog računala na FPGA sučelju (Undergraduate thesis). Rijeka: University of Rijeka, Faculty of Engineering. Retrieved from https://urn.nsk.hr/urn:nbn:hr:190:030908

Rogić, Vid. "Izvedba aritmetičko-logičke jedinice 8-bitnog računala na FPGA sučelju." Undergraduate thesis, University of Rijeka, Faculty of Engineering, 2023. https://urn.nsk.hr/urn:nbn:hr:190:030908

Rogić, Vid. "Izvedba aritmetičko-logičke jedinice 8-bitnog računala na FPGA sučelju." Undergraduate thesis, University of Rijeka, Faculty of Engineering, 2023. https://urn.nsk.hr/urn:nbn:hr:190:030908

Rogić, V. (2023). 'Izvedba aritmetičko-logičke jedinice 8-bitnog računala na FPGA sučelju', Undergraduate thesis, University of Rijeka, Faculty of Engineering, accessed 08 May 2024, https://urn.nsk.hr/urn:nbn:hr:190:030908

Rogić V. Izvedba aritmetičko-logičke jedinice 8-bitnog računala na FPGA sučelju [Undergraduate thesis]. Rijeka: University of Rijeka, Faculty of Engineering; 2023 [cited 2024 May 08] Available at: https://urn.nsk.hr/urn:nbn:hr:190:030908

V. Rogić, "Izvedba aritmetičko-logičke jedinice 8-bitnog računala na FPGA sučelju", Undergraduate thesis, University of Rijeka, Faculty of Engineering, Rijeka, 2023. Available at: https://urn.nsk.hr/urn:nbn:hr:190:030908

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Metadata
TitleIzvedba aritmetičko-logičke jedinice 8-bitnog računala na FPGA sučelju
Title (english)Implementation of the 8-bit arithmetic-logic unit on the FPGA board
AuthorVid Rogić
MentorIvan Volarić (mentor)
Committee memberDubravko Franković (predsjednik povjerenstva)
Committee memberIvan Volarić (član povjerenstva)
GranterUniversity of Rijeka
Faculty of Engineering
(Department of Automation and Electronics)
(Section of Electronics, Robotics and Automation)
Rijeka
Defense date and country2023-09-12, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Electrical Engineering
Abstract
Ovaj završni rad opisuje programski kod napisan u VHDL programskom jeziku koji simulira računalnu aritmetičko-logičku jedinicu, te njenu implementaciju na razvojnoj pločici FPGA uređaja. U radu su opisane komponente od kojih je sklop napravljen te su pobliže opisane sve cjeline s kojima se susrećemo. Posebna pažnja posvećena je konstrukciji aritmetičko-logičke jedinice od osnovnih logičkih komponenti te njihovoj međusobnoj povezanosti. U radu je izvršena računalna simulacija te praktična simulacija pomoću elektroničkih komponenti.
Abstract (english)
This bachelor's thesis describes a program code written in the VHDL programming language which simulates the computer’s arithmetic-logic unit along with its implementation on the FPGA device. In this thesis each component used to build this circuit is described in details. Special attention was brought into design of the arithmetic-logic unit using only basic logic units and their interconnections. This work also demonstrates computer simulation of this circuit as well as physical simulation done with electronic components.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:190:030908
Study programmeTitle: Undergraduate University Study of Electrical Engineering
Study programme type: university
Study level: undergraduate
Academic / professional title: sveučilišni/a prvostupnik/prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka elektrotehnike (sveučilišni/a prvostupnik/prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka elektrotehnike)
Type of resourceText
File originBorn digital
Access conditionsOpen access
Terms of useLicence Attribution 4.0 International (CC BY 4.0) icon
Created on2023-09-16 11:14:24